Ongoing trends in semiconductor device technology include miniaturization of feature size of semiconductor devices as well as increasing functional complexity of semiconductor devices. Although a feature size reduction may facilitate an increase in the number of semiconductor building blocks per unit area of a semiconductor device, e.g. a die or an integrated circuit (IC), thus facilitating more complex functionality per device, many demands for the increased functional complexity cannot be met by a single device.
Recently, this has led to the development of aggregate devices such as three-dimensional integrated circuits (3D ICs), also called multi-die ICs or hybrid ICs. One example of creating a 3D IC is to place active dies on a silicon interposer, which in turn is placed on a package substrate. The interposer provides die-to-die connections through micro-bumps on a first side of the interposer and die-to-package connections through bumps (or pads) on a second side of the interposer. The micro-bumps are connected by interconnects (or nets) through the interposer. The interposer further includes through-silicon vias (TSV) connecting the micro-bumps and bumps. The various micro-bumps, bumps, nets, and TSVs may include manufacturing defects and need to be tested.